[Original] Demystifying FPGA New Player EFINIX

提交于周四, 02/06/2020 Submitted by winniewei on Thursday, 02/06/2020
[Original] Demystifying FPGA New Player EFINIX

Author: Wisdom Zhang

At the 2019 FPGA Application Innovation Forum held by Electronic Innovation Network last year, a low-key FPGA new player aroused great interest. It was EFINIX. Why did Xilinx, the global leader in FPGAs, invest in this company? How bullish is its founding team? What's so unique about the new FPGA architecture they tinkered with? This article introduces you in detail.

Author Wisdom Zhang Contact Email: wisdomz@efinixinc.com

1. University of Toronto Computer Applications

In the 1998's, there were still many FPGA companies in semiconductors at that time, but Altera had already performed well in the market with its MAX series and FLEX series. At that time, Lattice urgently needed to own the genes of FPGAs. In order to get rid of the plight of only CPLD. Xilinx had a strong momentum at that time, basically speaking of FPGA, everyone understood directly as Xilinx's products.

In 2000, Altera started a product combining MAX and FLEX systems, called APEX, and they were determined to innovate, and the software was no longer satisfied with the use of a single user. Developed a new software name is Quartus, and there is a button inside, which can express the same interface as the previous Max + plus-II to please old users.

However, during the compilation process of the programmable device with APEX structure, the layout cannot be completed well. Although the chip, which appears to be very advanced on the surface, cannot perform well, Altera worked hard for a long time and did not improve it.

Later, an FPGA ox helped him solve the problem. He was Jonathan Rose of the University of Toronto , Canada. This old man has been committed to the research of FPGA structure design and software layout. Altera thinks that it can make Professor Rose's team Come and try it. So Jonathan started an EDA company specializing in FPGA structure design. This company was later acquired by Altera. Since then, Altera's FPGA structure design and software have become even more powerful, surpassing Xilinx and becoming the industry leader. Information about Mr Jonathan can be found

http://www.eecg.toronto.edu/~jayar/

Jonathan has brought a lot of students, many of them are very important doctrine founders and followers in the FPGA industry. His website also lists his students and some current achievements.

http://www.eecg.toronto.edu/~jayar/former-graduate-students.html

Vaughn Betz, one of the most influential students in the FPGA industry One of the most influential students in the FPGA industry, he has a brilliant experience in self-introduction

The VPR toolset and methodology developed by Dr. Betz have become the standard for FPGA architecture research and the comparison point for CAD optimization quality, and have been used by over 180 companies and 1100 universities. Dr. Betz co-founded Right Track CAD to commercialize his research in 1998 and over the next two years helped grow the company to 10 engineers and several million dollars in yearly revenue. In 2000, Right Track CAD was acquired by one of its customers, Altera Corporation (a fortune 500 semiconductor company). Dr . Betz held several leadership positions within Altera over the next 11 years,

There is also a promoter of Altera's university education program, Steven Brown

http://www.eecg.toronto.edu/~brown/

Another is Tony Ngai, Wei Qijie of EFINIX, and CTO of EFINIX.

Now the structural design of FPGA and the research and development frontier of place and route software have basically continued to improve at the University of Toronto, becoming the source of the most important theoretical practice in this industry.

Someone once counted that before 2008, at least 48 companies have been involved in the programmable device industry, but most of them have fallen into disrepair.

Demystifying FPGA new player EFINIX

Image Source:

http://www.ocoudert.com/blog/wpcontent/uploads/2009/10/History_of_PLD_startups.gif

Silicon is not Enough

--John Daane, CEO, Altera

A large number of companies entered and finally came back. The implication behind it is that only a chip is not enough. You must also have good logic to develop software, and this development software must cover many aspects of EDA software. The cost and trial and error cost are very high, and the entire industry is rapidly competing and iterating, not only in process improvement, but also in structural design, benchmark selection, and IP integration, it can be said that basically every aspect cannot Make mistakes. However, the development of a brand new product basically requires a three-year development cycle, plus the need to continuously maintain and upgrade complex development tools. All in all, the Phoenix must survive.

But after 2008, there are still several companies entering this industry. The more famous ones are Tabula, SiliconBlue, and Tabula disappeared after burning out a billion dollars. SiliconBlue was also acquired by Lattice, so you want to enter this industry, and To survive, at least you have to dare to challenge the existing environment and do have your own innovation. At the same time, many achievements and habits of the industry must also be considered, and the existing resources should be used as much as possible instead of rebuilding the wheels. Under this background, EFINIX company has come. What is unique about it?

2.EFINIX's unique skills

EFINIX CEO Zhang Shaoyi went to study in the United States from Hong Kong in the early years. He was the Stratix Product Director of Altera's high-end FPGA. During this period, he was responsible for Hardcopy's R & D engineering work with Mr. Wei Qijie. They later founded EFINIX together, and at the same time invited Jay who had been involved in the research and development of Maxplus-II to help out.

In 2015, they started their chip manufacturing plan in China, cooperated with SMIC, and packaged in Shanghai. The entire industrial chain took root in China.

EFINIX Hong Kong Company is the operating entity, with Penang Malaysia as the main R & D base, and software and technical engineering resources are also established in Hong Kong. Attract Chinese capital. There are several well-known VC investments.

As a CTO, Mr. Wei Qijie had many ideas in the early years, but these ideas had to undergo long-term modeling tests and verification development of test chips. After 6 years, the industry's inherent thinking was broken, and a new type of FPGA innovative architecture was created and verified.

Myths in the FPGA Industry

Usually in an industry that has been in development for a relatively long time, it is not easy to have innovations, because there are many patent barriers, and people do not have much resources to verify whether such innovations are effective. In addition, many innovations may be abandoned in the past. Already achieved, EFINIX as a new company, he may not have too much burden in this regard.

They believe

Hard to survive without innovation

Demystifying FPGA new player EFINIX

Today's FPGAs are basically island-type structures, and even many chips use the LUT6 structure. Four, nine, or more such large lookup tables are integrated in a small area. I hope these LUT6s with the same function Put together, it can quickly solve some 8-bit, 9-bit register groups or counters, shift counters, etc. Therefore, as the scale of the chip continues to rise, the connection resources between the logical resource groups also rise rapidly. Sometimes it is conceivable that the resources that may be routed on the purchased programmable chip exceed the actual effective logical resources. Let's use a city as an image metaphor.

Demystifying FPGA new player EFINIX

With the expansion of cities, wider roads must be established, and many larger interchanges must be established between the roads, and the levels of these interchanges may be complex, and more traffic lights and ramps are required to converge and separate Traffic flow. These are actually very similar to the structure of an FPGA. You can naturally think that the larger the chip size, there are only two ways to complete the interconnection and interconnection between logic. Either increase the routing resources by many layers, or increase the area of the chip to increase wiring. Even both aspects need to be strengthened.

These practices directly lead to greater power consumption of the chip and larger chip area. Through continuous analysis and simulation of the adaptation of various designs on the FPGA of the previous structure, it was found that some areas consume more logic resources and some areas have more connections, so even if there are free wiring resources elsewhere, they cannot Bring a good compromise. As a result, the higher the utilization rate of the chip, the more difficult it is to meet the expected target timing conditions. Otherwise, choose a larger capacity chip to alleviate this situation.

Demystifying FPGA new player EFINIX

Many designers design with FPGAs that are 30% larger than expected. This is all cost, this is all power consumption, and these are all latency.

Demystifying FPGA new player EFINIX

To alleviate this contradiction, Tony came up with a good solution, which summarizes the following two principles.

First, a smaller and finer-grained structure is used to remove the connection overhead of too many logical groups and logical groups from access and fan-out, so that the wiring between logic and logic is significantly shortened, even if some jumpers are added, but the overall delay The structure of time and the past is equivalent, and the future will be better adapted to this idea,

Then, the logical resources and wiring resources can be transformed into each other, so that related logic is aggregated as much as possible, and the timing is correspondingly improved. In this way, we can imagine that the compilation software is like a construction company. Where roads are needed, houses can be demolished, and The road is widened, and in some places, the road can be built into a house. The combination of these two methods can finally make

EFINIX's Trion series FPGAs only require 7 metal routing layers, while traditional FPGA structures require more than 12-14 layers.

At the same time, due to the use of a fine-grained structure, a lot of unnecessary wiring access and fan-out overhead are eliminated, so that the chip has an advantage of 1/3 to 1/2 area reduction compared with the traditional structure at the same scale.

In the end, EFINIX's Trion series FPGAs not only have very small power consumption, but also have smaller packages. It also has a cost advantage. At the same time, SMIC's 40nm low-power process is used. The T8 can support 8K logic capacity FPGA with 30mW, and the T120 can accommodate 115K logic capacity FPGA. The typical application power consumption is only 1.3W. This is the company's biggest innovation in the field of FPGAs. Because this kind of innovation is not adopted, it is difficult to shake the industry status of the giants in the industry, and it is difficult to stand out and gain a competitive advantage.

In order to achieve lower power consumption and focus on the video and camera markets at the same time, the MIPI hard interface is integrated in the FPGA, and the DDR3 controller also uses a hard core. This design method further reduces chip size and further reduces power consumption.

EFINIX is not only forward-looking in terms of the architecture design of logic devices. Tony can better integrate the structure of its own design with the routing algorithm layout of the FPGA, thereby completing the unified demand for efficiency. Speaking of CAD tools for programmable devices, everyone knows that Foundation, ISE, Quartus-II, and EFINIX independently completed the entire EDA software design tool. Jay has accumulated many years of experience in the EDA field, and deeply realized that it is important for the company itself and customers to be able to quickly iterate and continuously shorten the time to market when new devices are continuously launched.

The name of EFINIX's design software is Efinity. The logo of the software has the characteristics of the two dragons of Eastern culture. The company that implies FPGA must not only have a strong hardware architecture, but also the software is an important foundation. The P & R algorithm in Efinity software is designed based on its own product architecture. Unlike many softwares, the software supports Hybird's P & R algorithm because of the special structure.

With this innovative architecture and its own logical layout and logical routing features that can be interchanged, EFINIX successfully broke the myth of the previous FPGA structure design, using an area advantage of nearly half that of competitors to design equivalent capacity FPGA products. And the advantages of this structure can also effectively shorten the development time for the introduction of new products. In one year, the development of the first Trion product was completed with less than 1/10 of the human resources of the opponent.

EFINIX gives this innovative structure an associative name, Quantum, like the magical meaning of quantum technology. We summarize the changes brought about by this:

Under the same process conditions, the area is reduced by 2 times or more

Reduce power consumption by half

The chip uses a 7-layer metal process

Can use universal silicon process without any customization

Have the same logic speed performance as FPGA under the same process conditions

Can use Hybird's layout

Demystifying FPGA new player EFINIX

Today's FPGA applications, everyone expects a large logic capacity, but the area must be small, performance cannot be sacrificed, and power consumption must be very competitive. As a startup company, users always have quality concerns, but the reliability and consistency of these products ultimately require an experienced team with a complete design process to ensure it. And software development needs enough time to test. After EFINIX has invested a lot of time in the past 6 years, it can launch the complete Trion series in just one year.

The evenly distributed wiring resources are often difficult to meet the local wiring requirements of the actual design

Demystifying FPGA new player EFINIX

• Partial blockage (red area) is the short board of the entire chip

• Idle resources (green area) cannot be moved and can only be wasted

• Increasing overall wiring resources can alleviate local blockages, but cause greater waste in other areas

3. Comparison of products

What is the product of "sister-in-law and horse-drawn "? It needs to be compared and contrasted. At present, the development of a product depends not only on whether the current product meets market demand, but also the externally developed product must have rapid development capabilities. Both have adopted a platform-based approach. EFINIX company uses a unified architecture to quickly conduct product pre-research at the software level. Because it uses a special structure that can transform routing, it can make up for the irreversible development dilemma of chip growth, but insufficient routing resource planning . Before the product is developed, it is basically possible to predict the performance of the product and test the Benchmark use cases. In the past product development of FPGA companies, it is difficult to continue to use the same process for products with 40nm technology to 100K logic resources. However, due to the competitive advantage of the Trion series in chip size, EFINIX can still develop devices with logic resources of 165K and 200K on 40nm mature technology.

The current development means must have better performance prediction capabilities. Excellent design teams always make full use of the company's CAD to perform the process evolution of next-generation FPGAs and current competitors and their own products to estimate performance and power consumption. In order to obtain the best product investment benefit ratio.

We show a part of the Benchmark design used in the development, and benchmarked the competitors' products with the following performance and utilization comparisons. The following figure is a comparison. It can be seen that the silicon process, the same performance, and the advantages of the Hybird P & R platform are obvious.

Demystifying FPGA new player EFINIX

Interface Designer Interface Wizard

As a latecomer in the field of FPGA, although FPGA is a programmable chip, but focusing on the market and having a higher cost performance, it is possible to distance itself from the price of similar products in the new design. EFINIX's Trion series FPGAs are targeted at the target market by hard-core IP design of common functions, which can effectively reduce the size of the chip on the one hand and reduce power consumption on the other. At the same time, a relatively streamlined function is used to support IO, which effectively reduces the on-chip area of IO, and can integrate more IO on a smaller chip.

Demystifying FPGA new player EFINIX

For example, it is the first to hard-core the MIPI CSI-2 controller. It can provide MIPI interface integration on a 40nm low-cost FPGA, and developers only need to configure the protocol parameters they need. Popular image sensors are docked, because the development of AI SoC is very fast, and the image sensor interface of AI-SoC is mainly based on MIPI access. Although the application of multiple sensors has been popularized on mobile phones, it is used in embedded and AI applications. There are also more Sensor accesses, so Trion series FPGAs can support 2 to 3 MIPI accesses, and at the same time converge or cross to the MIPI interface of the AI SoC, which can expand MIPI or cross MIPI capabilities.

There is also a very good and universal example. Different chip sizes integrate different DDR3 hard core controllers with different bit widths, which not only reduces power consumption, but also supports FPGAs with different bandwidth requirements.

Demystifying FPGA new player EFINIX

The Trion series has a different approach for LVDS applications for FPGAs. The general practice in the industry is that each IO supports LVDS as much as possible. It seems to be flexible in configuration. However, the area occupied by the IO on the chip is too large, which can not effectively increase the IO and power consumption It was also a challenge. Trion series of LVDS has been pre-defined with fixed input and output directions. Ensuring the smallest IO area can reduce power consumption, and also focus on Sensor applications in the number of LVDS support. Based on 13 Rx LVDS considerations, ensure that most image applications can not only use LVDS access, but also MIPI Access, really achieve the functional design of a sensor manager.

Demystifying FPGA new player EFINIX

The above design updates are only connected to the actual HDL design, but do not involve HDL design methods. At the same time, in order to meet the SoC design methodology, the digital logic core and peripheral interface parts are isolated and abstracted, separated and developed. EFINIX Efinity software uses the industry's unique interface design wizard. Put all hard-core IP in the interface of Interface Designer, and the digital core that focuses on logic design belongs to the core logic design. Such design module isolation and abstraction can greatly reduce the workload of platform development. FPGA products If the classification is based on the logic capacity of the FPGA and the IO interface, then a series of FPGA products can be considered as two combined designs with different device logic capacity and different interface types. The separation of the interface designer design allows These two factors are quickly combined and matched. Because FPGA products of the same density may have different peripherals, users can see the support of the hard IP that can be supported in Interface designer automatically.

Another advantage of this is that when there are large-scale customers using SiP or eFPGA projects, they can simply modify the Interface designer to complete the development of custom eFPGA software.

The interface designer interface wizard now has the following support according to different devices and different packages of the same device

In November 2019, EFINIX launched T120, a highly competitive 40nm power product. This product shows EFINIX as a rookie in the industry, showing that it can launch products larger than 100KLE, and at the same time, it can increase the utilization rate to nearly 100%, and Limit power consumption to between 1.2W and 1.5W. Power consumption is half lower than competitors with the same level of technology, or even 1/3 of competitors. The package is a 12x12mm FBGA. The product is favored in applications with limited size and limited power consumption.

4: China market breakthrough

China has undoubtedly become the world's largest FPGA developer and the largest single market for FPGA applications. China's application market opportunities have accounted for more than 40% of the global FPGA market. To be a latecomer, if you want to gain a place in the Chinese market, you must have products and technical resources suitable for the Chinese market and users.

EFINIX understands that time is life and efficiency is money. The Chinese market principle cannot be developed and supported quickly, and there will be no way to survive. In addition to innovation that breaks myths, in the minds of consumers, the most suitable principle for quickly establishing a product and corporate image

The Chinese market, but not fast

In the past 12 months, EFINIX relied on a team of 35 people to successfully launch 8 products, from 4K logical density 3x3mm products to 120K FBGA576 16x16mm large-capacity products. And compile and synthesize, the layout software is based on independent development. Really reflects the fastest delivery speed. And in the next time, more large-scale 165K and 200K products will be available. Provide solutions for today's applications that require edge AI.

Demystifying FPGA new player EFINIX

Targeted market

At the same time, in the face of the fast-changing Chinese market and the full competition of many FPGA companies, EFINIX is currently focusing on specific markets, supporting software IP, and focusing on applications, and has been recognized by customers in the following markets.

Industrial camera market

Special camera application HDR

VR glasses

Capacitive pen

Industrial PLC

Industrial servo control

Industrial laser control

Display stitching control

5.Application of RISCV

Demystifying FPGA new player EFINIX

RISCV is a hot topic recently for embedded applications worldwide, because of its open source and simple structure, and excellent energy efficiency. In just two years, many companies have launched MCUs in the RISCV system in the Chinese market. The main inherent MCU market brings new challenges. And RISCV can also be quickly matched with a variety of peripheral resources, which is a very good choice for AIoT applications. Very well made up for the needs of the fragmented application market.

Due to the extremely flexible characteristics of FPGAs, industry leaders in the past FPGA field have their own soft-core CPU tools, such as NiosII from Altera Corporation and MicroBlazer from Xilinx Corporation. The design interfaces and concepts are different. FPGA companies pose great challenges because there are many designs that require soft cores. Latecomer CPU soft cores must not only be easy to use, fast to get started, and performance can effectively compete. Such options are actually not many.

The emergence of RISCV has greatly facilitated the need for soft cores in FPGAs. An important issue here is that although RISCV is a set of systems, the IP provided by each RISCV is not suitable for application in FPGAs. For example, many domestic IP supplies Vendors, the RISCV provided on the FPGA may consume resources ranging from 30K to 75KLEs. How to launch the RISCV system has relatively reasonable resources in the FPGA, and its performance is stronger than traditional soft-core CPUs such as NiosII, and the tool chain is closer to the development method of the ARM system. Moreover, the supported peripherals and RISCV execution space can not only run short and powerful programs in the block RAM of the FPGA, but also large FreeRTOS in the DDR, which also involves the effective design of the bootloader.

EFINIX launched multiple RISCV IPs, which can take into account the application of soft cores in different FPGA scales. Now it is possible to embed RISCV in a full range of Trion, as small as T4 and as large as T120, and it can also support the embedded design of multiple soft cores. In the 16-bit and 32-bit designs of DDR3, the interface design of RISCV has been successfully completed. Not only can RISCV run in DDR3, but some versions can support D-Cache and I-Cache, making it suitable for applications that require higher performance. Occasions can also cover demand. The consumption of logical resources is controlled at 9KLEs, which achieves a good system integration.

references:

Mr. Vaughn's introduction:

http://www.eecg.toronto.edu/~vaughn/biography.html

Jonathan Rose introduces:

http://www.eecg.toronto.edu/~jayar/

Steven Brown introduced:

http://www.eecg.toronto.edu/~brown/

There is also a video presentation by the author here.